A conventional CMOS reference voltage circuit is described in detail in Patent Document 1 (JP Patent Kokai Publication No. JP-A-11-45125). This reference voltage circuit obtains a reference voltage through current-to-voltage conversion. This is of course the same as with a reference voltage circuit of this type devised before by which the temperature characteristic of the reference voltage is compensated. In the reference voltage circuit of this type devised before, by which the temperature characteristic is compensated, a reference voltage having a positive temperature characteristic is converted to a voltage by an output circuit constituted from a resistor and a diode (or a diode-connected transistor). A voltage component representative of a voltage drop across the resistor having a positive temperature characteristic and a voltage component representative of a forward voltage of the diode (or the diode-connected transistor) having a negative temperature characteristic were obtained. Then, by adding both of the voltage components, the reference voltage of approximately 1.2 V with temperature characteristic thereof compensated is obtained.
On the other hand, in the reference voltage circuit described in Patent Document 1 (Japanese Patent Kokai Publication No. JP-A-11-45125), which was devised by Mr. Bamba, a reference current having little temperature characteristic is obtained, and the reference current is converted to a voltage by an output circuit constituted from a resistor alone. The reference voltage having an arbitrary voltage value is thereby obtained.
The voltage of 1.2 V with the temperature characteristics thereof compensated, defined as the output voltage of the conventional reference voltage circuit of this type, is obtained through conversion to current value within the circuit. Thus, the reference voltage circuit can be operated at a supply voltage of 1.2V or less.
Non-patent Document 1 (“Analog Circuit Design Technique for CMOS Implementation of A Portable Radio Terminal”, by Triceps Co., Ltd., 1999), which is a text written by the inventor of the present invention, immediately introduced this circuit as a “current-mode reference voltage circuit” before the end of the year when the circuit was disclosed, and published a detailed circuit analysis thereof.
In the conventional reference voltage circuit, in particular, the forward voltage of the diode (or diode-connected transistor) is used as the voltage component having the negative temperature characteristic. Accordingly, a deviation from the temperature characteristic of the forward voltage of the diode (or diode-connected transistor) noticeably appears in the output voltage.
That is, the forward voltage of the diode (or the diode-connected transistor) has the negative temperature characteristic, and as the temperature is reduced, the gradient of the negative temperature characteristic becomes gentle.
On the other hand, the voltage having the positive temperature characteristic is implemented by obtaining a current that flows through the resistor using a difference voltage between the forward voltages of two diodes (or diode-connected transistors) having different current densities, and further converting the current into the voltage by the resistor.
It should be noted herein that, since the gradient of the negative temperature characteristic of the forward voltage of the diode (or diode-connected transistor) becomes gentle as the temperature is lowered, linearity of the forward voltage of the diode with respect to the temperature characteristic is poor, but linearity of the difference voltage between the forward voltages of the two diodes (or diode-connected transistors) (having the different current densities) with respect to the temperature characteristic is very good. This is not described in the above-mentioned text.
As described above, even if devices each having poor linearity with respect to the temperature characteristic are used, by changing the circuit configuration of the reference voltage circuit to the current-mode reference voltage circuit and by using the difference voltage between the devices, the linearity with respect to the temperature characteristic is greatly improved.
An operation of the reference voltage circuit will be described according to contents described in Patent Document 1 (Japanese Patent Kokai Publication No. JP-A-11-45125). Referring to FIG. 1, by an OP amp DA1, a common gate voltage of transistors P1 and P2 is so controlled that a voltage VA equals to a voltage VB.
Accordingly, the following equation holds:VA=VB  (1)
Further, the following equation holds:I1=I2  (2)
The output current I1 of the p-channel transistor P1 is branched into a current I1A that flows through a diode D1 and a current I1B that flows through a resistor R4. Likewise, the output current I2 of the p-channel transistor P2 is branched into a current I2A that flows in common through a resistor R1 and diodes D2 and a current I2B that flows through a resistor R2. The resistor R1 is connected in series with the p-channel transistor P2, and the diodes D2 are constituted from N diodes connected in parallel to one another.
WhenR2=R4  (3)
thenI1A=I2A  (4)I1B=I2B  (5)
hold.
When the forward voltages of the diodes D1 and D2 are represented by VF1 and VF2, respectively, the following equations are derived.VA=VF1  (6)VB=VF2+ΔVF  (7)
Then, the following equation holds:ΔVF=VF1−VF2  (8)
The ΔVF indicates a voltage drop across the resistor R1. Thus, the following equations hold:I2A=ΔVF/R1  (9)I1B=I2B=VF1/R2  (10)
Here, the following equation holds:ΔVF=VT ln(N)  (11)
in which VT indicates a thermal voltage, and is expressed as follows:VT=kT/q  (12)
where T is absolute temperature in degrees Kelvin [K], k is Boltzmann's constant, and q is the charge of an electron.
Accordingly, a current I3 (=I2) is converted to a voltage by a resistor R3, and a voltage Vref is expressed as follows:
                                                        Vref              =                              R                ⁢                                                                  ⁢                3                ×                I                ⁢                                                                  ⁢                3                                                                                        =                              R                ⁢                                                                  ⁢                3                ⁢                                                                  ⁢                                  {                                                            VF                      ⁢                                                                                          ⁢                                              1                        /                        R                                            ⁢                                                                                          ⁢                      2                                        +                                          (                                                                        V                          T                                                ⁢                        ln                        ⁢                                                                                                  ⁢                                                                              (                            N                            )                                                    /                          R                                                ⁢                                                                                                  ⁢                        1                                            )                                                                                                                                              =                                                (                                      R                    ⁢                                                                                  ⁢                                          3                      /                      R                                        ⁢                                                                                  ⁢                    2                                    )                                ⁢                                  {                                                            VF                      ⁢                                                                                          ⁢                      1                                        +                                                                  (                                                  R                          ⁢                                                                                                          ⁢                                                      2                            /                            R                                                    ⁢                                                                                                          ⁢                          1                                                )                                            ⁢                                              (                                                                              V                            T                                                    ⁢                          ln                          ⁢                                                                                                          ⁢                                                      (                            N                            )                                                                          )                                                                              }                                                                                                         (        13        )            
In which a voltage (VF1+(R2/R1)(VT ln(N)) has the value of approximately 1.2 V with the temperature characteristic compensated. Specifically, the voltage VF1 has a negative temperature coefficient (temperature characteristic) of approximately −1.9 mV/° C., while the voltage VT has a positive temperature coefficient of 0.0853 mV/° C. Accordingly, in order to compensate the temperature characteristics, the value of (R2/R1)ln(N) becomes 22.3.
Since the thermal voltage VT is 26 mV at an ambient temperature (300K), a voltage (R2/R1)(VT ln(N)) becomes approximately 580 mV at the ambient temperature.
Accordingly, when the voltage VF1 is set to 620 mV at the ambient temperature, the voltage {VF1+(R2/R1)(VT ln(N))} becomes approximately 1.2 V.
The temperature characteristic will be rigidly discussed. Since the resistor R4 is connected in parallel with the diode D1, the value of a current that flows through the resistor R4 tends to decrease due to non-linearity with respect of the temperature characteristic of the diode.
On the other hand, the resistor R1 is connected in series with the diode D2. Thus, when a current that flows through the diode D2 has a positive temperature characteristic, a voltage between the diode D2 and the resistor R1 will be lower than the voltage of the diode D1.
Since the voltages of both of the diodes are controlled to be equal, an increase in the currents is performed at a low temperature, thereby operating so that voltages at both of the diodes to be equal. Conversely, at a high temperature, an inverse operation is performed.
That is, each of the currents that flow through the diodes D1 and D2, respectively, in this circuit are set to have a temperature characteristic smaller than the temperature characteristic defined by (VT ln(N))/R1. Currents (VF1/R2, VF1/R4) that flow through the resistors R2 and R4, respectively, also increase at the low temperature to a certain degree.
Drive currents supplied from the transistors P1, P2, and P3 function to cancel non-linearities with respect to the temperature characteristics of the forward voltages of the diodes. Thus, the temperature characteristic of the reference voltage obtained can also be set to the characteristic which is very close to a straight line having less variations with respect to the temperature.
Since a resistor ratio (R3/R2) has zero temperature coefficient, the reference voltage Vref to be output becomes the voltage in which the temperature characteristics thereof are compensated.
The resistor ratio (R3/R2) can be arbitrarily set. When the ratio (R3/R2) is larger than 1, the voltage Vref becomes the voltage higher than 1.2 V. When the ratio (R3/R2) is smaller than 1, the Vref becomes the voltage lower than 1.2 V.
In Patent Document 1 (Japanese Patent Kokai Publication No. JP-A-11-45125), the value of 10 is described as the specific value of N. However, when the circuit was actually implemented, N was set to 100 (according to an IEEE Symposium on VLSI Circuits 1998 (May)).
The miniaturization in CMOS process has advanced, and the size of MOS transistors has become smaller. On contrast therewith, the size of a diode that employs a parasitic bipolar device is enormously larger than that the MOS transistor.
The ratio N between the diode D1 and the diode D2 is increased substantially from a single-digit number to a double-digit number, the areas of the diode D1 and the diode D2 on a chip have become large.
Meanwhile, each of Patent Documents 2 and 3 discloses a CMOS reference voltage generating circuit including a first voltage generating circuit, a second voltage generating circuit, an output resistor element, an operational amplifier OP, transistors PT1, PT2, and PT3, and current sources IS1, IS2, and IS3. The first voltage generating circuit includes a diode D1 and generates a voltage VN1 for the diode D1. The second voltage generating circuit includes a diode D2 and generates a voltage VN2 for the diode D2. The operational amplifier OP performs feedback control so that the voltage VN1 is generally equal to the voltage VN2. Gate electrodes of the transistors PT1, PT2, and PT3 are controlled by the operational amplifier OP, thereby controlling currents to be supplied to the first voltage generating circuit, second voltage generating circuit, and output resistor element. The current sources IS1, IS2, and IS3 supply currents for activating the CMOS reference voltage generating circuit to the first voltage generating circuit, second voltage generating circuit, and output resistor element, respectively.    [Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-11-45125    [Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2003-173212A    [Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2003-173213A    [Non-Patent Document 1]
“Current-mode Reference Voltage Circuit” by Kimura, “Analog Circuit Design Technique for CMOS Implementation of A Portable Radio Terminal”, by Triceps Co., Ltd., 1999